FIG. 9 is a cross-sectional view of a prior art process for producing an N channel MOSFET. In the figure, reference numeral 1 designates a P(P.sup.-)-type semiconductor substrate, reference numeral 2 designates a gate oxide film disposed on the substrate 1, and reference numeral 3 designates a gate electrode comprising a refractory metal or polycrystalline silicon disposed on the gate oxide film 2. Reference numerals 6d and 6e respectively designate a source-side N-type region and a drain-side N-type region, both produced by implanting a dopant impurity, such as phosphorus or arsenic, employing the gate electrode 3 as a mask.
FIGS. 11(a) and 11(b) are cross-sectional views of a prior art process for producing a lightly doped drain (hereinafter referred to as LDD) MOSFET that has been employed for suppressing variations in threshold voltage and reductions in the breakdown voltage in a MOSFET having a shortened gate length. In FIG. 11(a), reference numerals 9 designate side walls produced at both sides of the gate electrode 3 by, after processing the gate electrode 3, producing an oxide film on the entire surface of the substrate 1 and removing this film by anisotropic etching. Reference numerals 4c and 4d respectively designate a source-side N.sup.- -type region and a drain-side N.sup.- -type region, both produced by rotational implantation at an inclination angle, of a dopant impurity, such as phosphorus or arsenic, employing the gate electrode 3 and the side walls 9 as a mask. Reference numerals 6b and 6d respectively designate a source-side N-type region and a drain-side N-type region, both produced by implanting a dopant impurity, such as phosphorus or arsenic, with a higher concentration than the source-side N.sup.- -type region 4c and the drain-side N.sup.- -type region 4d, employing the gate electrode 3 and the side walls 9 as a mask.
In FIG. 9, the gate oxide film 2 on the P-type semiconductor substrate 1 is several tens of nanometers thick and is produced by thermal oxidation of the surface of the substrate 1. A refractory metal film or a polycrystalline silicon film several hundred nanometers thick is produced on the entire upper surface. The gate electrode 3 has an approximately 1 .mu.m gate length. Next, the source-side N-type region 6d and the drain-side N-type region 6e are produced by implanting a dopant impurity, such as phosphorus or arsenic, employing the gate electrode 3 as a mask. Thereafter, the structure is annealed, completing all production processes.
When a positive voltage is applied to the drain electrode 20, the source electrode 30 is grounded, and a positive voltage is applied to the gate electrode 3, the P.sup.- -type semiconductor substrate 1 directly below the gate electrode 2 is inverted to N-type and the device operates as a MOSFET. When a reverse direction voltage is applied between the drain electrode 20 and the source electrode 30, the highest electric field is the drain-side N-type region 6e directly below the gate electrode 3 and can produce an avalanche breakdown. When the dopant impurity concentration of the P.sup.- -type semiconductor substrate 1 is lower than the dopant impurity concentration of the drain-side N-type region 6e, the depletion region from the drain-side N-type region 6e reaches the source-side N-type region 6d, causing punch-through breakdown. The threshold voltage applied to the gate electrode 3 is determined by the dopant impurity concentration of the P.sup.- -type semiconductor substrate 1 and the thickness of the gate oxide film 2.
In the structure of FIG. 10, when the length of the gate electrode 3 is no more than 1 .mu.m, avalanche breakdown and punch-through breakdown become significant so that no MOSFET having a practical breakdown voltage can be made. Furthermore, there are equipotential surfaces curving directly below the gate electrode 3, as shown by broken lines in FIG. 10, resulting in a reduction in the threshold voltage. The equipotential surfaces result in unstable switching so that the rated operation is difficult to realize and high frequency isolation characteristics deteriorate. While the above description pertains to an N-type MOSFET, in a P-type MOSFET, the rated operation is also difficult to realize due to a rise in the threshold voltage that causes unstable switching.
One prior art solution to this problem is the so-called LDD structure. As shown in FIG. 11(a), after processing the gate electrode 3, an oxide film (not shown) is deposited on the entire surface of the semiconductor substrate. Portions of the oxide film at both sides of the gate electrode 3 remain after anisotropic etching because the thicknesses of these portions of the oxide film are larger than the oxide film located at flat portions of the substrate spaced from the gate electrode 4. These remaining portions at both sides of the gate electrode are employed as side walls 9. After producing the side walls 9, the source-side N.sup.- -type region 4c and the drain-side N.sup.- -type region 4d are produced by rotational ion implantation of a dopant impurity, such as phosphorus, at an inclination angle and employing the gate electrode 3 and the side walls 9 as a mask.
Subsequently, as shown in FIG. 11(b), the source-side N-type region 6b and the drain-side N-type region 6d are produced by rotational ion implantation with an inclination angle of 0.degree. or 7.degree. between the substrate surface and the direction of incidence of a dopant impurity, such as phosphorus or arsenic. The implantation produces a higher dopant impurity concentration than in the source-side N.sup.- -type region 4c and in the drain-side N.sup.- -type region 4d, produced as described above, and employs the gate electrode 3 and the side walls 9 as a mask.
When a positive voltage is applied to the drain electrode 20, which is produced in a subsequent production process not shown in FIG. 11(a), with the source electrode 30 grounded, the electric field is relaxed by the source-side N.sup.- -type region 4c directly below the gate electrode 3. Therefore, avalanche breakdown and punch-through are suppressed. In addition, the radius of curvature of the equipotential electric field surface directly below the gate electrode 3 when a reverse direction voltage is applied is increased by the source-side N.sup.- -type region 4c and the drain-side N.sup.- -type region 4d, reducing the threshold voltage for a particular gate voltage.
Because the prior art field effect transistor is structured as described above, a reduction in the breakdown voltage accompanying the shortening of the gate length is unavoidable, resulting in difficulty in suppressing a reduction in the threshold voltage. When the LDD structure is adopted as a solution to these problems, a considerable improvement is obtained in a general IC circuit but, when an LDD structure is employed in a circuit operating at high power and a high frequency, it is difficult to obtain a satisfactory improvement. While it is known that reductions in breakdown voltage and threshold voltage are suppressed by increasing the substrate dopant impurity concentration, this method causes a reduction in the mobility of electrons in a channel directly below the gate electrode, resulting in difficulty in realizing high speed operation.
Japanese Published Patent Application Sho. No. 62-95873 discloses a MOSFET having a gate with a gate length of no more than 1 .mu.m in which a drain-side low dopant impurity concentration region that is effective in relaxing a high electric field is lengthened and the source-side low dopant impurity concentration region that reduces device performance is shortened. According to the method described in the publication, ion implantation producing the source region is performed employing the same mask as that employed in producing the source-side low concentration region, causing variations in the size of the source-side low concentration region that is actually obtained, resulting in low manufacturing precision. In addition, the dopant impurity concentration in the source-side region is higher than in the drain-side low dopant concentration region so that the gate overlapping capacitance is large and the source-drain breakdown voltage is insufficient.